HSPICE 2013.12 – Major Enhancements in December 2013 Release Fundamentals. BSIM-CMG model evaluation runs 50% faster than the 2013.03 release, enabling faster simulation of FinFET-based circuits.

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This applies to both built-in and Verilog-A BSIM-CMG models. Users can specify different RUNLVL values for different subcircuits and instances in the design hierarchy, enabling the speed-up of non-critical blocks, such as digital control, without compromising overall accuracy. Users can run Monte Carlo analysis of SRAM bit cells using one billion samples distributed over multiple CPUs on the network. The Monte Carlo results are achieved using accurate SPICE Monte Carlo and can be used as a golden reference to verify the results of fast Monte Carlo methods. 1.5X faster simulation of large post-layout circuits compared to 2013.03 release Signal Integrity. 1.5X speed-up of S-elements with over 100 ports, enabling faster transient analysis of large-scale systems, such as complex IC packages. The feature is qualified up to 600 ports New Models.

FinFET BSIM-CMG 1.07 (level 72). BSIM6 6.0, 6.1beta2 (level 77). BSIM 4.8 (level 54). UTSOI 1.14f, 2.00g (level 76). PSP103.2 w/I self-heating (level 69). HiSim-HV 1.24.

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HiSim-HV 2.10. Hicum 1.31, 2.32. Mextram 504.10.1, 504.11 MOS Reliability Analysis (MOSRA) now supports FinFET BSIM-CMG models Documentation.

Users can use the '-help' option from the command line to access the online help topics. HSPICE 2012.06 – Major Enhancements in June 2012 Release HSPICE for Analog. Harmonic Balance analysis now supports multi-threading to deliver up to 4X speed up on 8 cores, enabling fast and accurate steady state analysis Signal Integrity. New S-element implementation speeds up the transient analysis of long-delay systems such as backplane traces and HDMI cables. Simulation of long bit patterns (e.g., 60,000 bits) can be up to 60X faster than 2011.09 release with no compromise of HSPICE golden accuracy Multi-technology Simulation.

Multi-technology simulation (MTS) allows the simulation of different chips of different technologies in the same run without modifying the netlist, models or parameters of the individual chips. This technology will enable the simulation of 3D integrated circuits and silicon interposer packages. New Models.

FinFET BSIM-CMG 105.031, 105.04, 106.0. BSIM6. HiSIM-HV 2.0.0. Mextram 504.10. HSPICE 2010.12 – Major Enhancements in December 2010 Release. HSPICE Precision Parallel (HPP) technology HPP is a new multi-threading technology that delivers up to 7X simulation speed-up for analog and mixed-signal designs. The technology scales effectively up to 8 cores and can handle post-layout circuits larger than 10 million elements.

To learn more about HPP technology, please. HSPICE distributed processing (DP) Improve the throughput of corner case analysis, Monte Carlo, and parametric sweeps by automatically distributing the job on a cluster of machines. Distribution takes place directly from an HSPICE netlist and does not require a third-party load-balancing infrastructure. The distributed processing throughput scales linearly with the number of CPUs, reaching 17X on 20 CPUs. Jitter measurement in HSPICE transient noise analysis Jitter is efficiently calculated in reasonable simulation times using either the Monte Carlo or Stochastic Differential Equations (SDE) method coupled with post-processing in Custom WaveView. The overall performance of transient noise analysis in the 2010.12 release has improved 3X over the previous release.

The overhead of running transient noise analysis is only 3X a plain transient run. New selective-net back-annotation flow The flow significantly improves post-layout simulation performance by attaching parasitics only to active nets in the design. Active nets are automatically identified using the active net check in CustomSim. Statistical analysis ACMatch, DCMatch and advanced Monte Carlo analysis, originally available with the Variation Block, now also support the traditional HSPICE parameter distribution functions (e.g., AGAUSS). Signal Integrity.

3X field solver performance improvement, enabling faster analysis of complex traces at more frequency points. Graphical visualization of W-element cross sections. Unfolding of statistical eye diagrams to examine the waveforms and analyze crosstalk at specific time points. Touchstone 2.0 support. Enabling native mixed-mode S-parameter support and explicit frequency sampling point declaration. Support of HSPICE parameters in IBIS 5.0 Algorithmic Modeling Interface (AMI), enabling sweep and parametric analysis of AMI models New syntax and models.

BSIM-CMG 104.0. BSIMSOI 4.3.1. HICUM 2.24.

Support for case-sensitive netlist formats. HSPICE 2010.03 - Major Enhancements in March 2010 Release Performance, Convergence, Capacity & Accuracy Improvements. Improved single-core & multi-threaded runtime performance on large pre- and post-layout circuits.

2X on 1 core + scaling to 8 cores Analog/RFIC Design. Loop stability analysis. Enhanced back-annotation flow. Design for yield—extended variability analysis Signal Integrity. IBIS 5.0—AMI support in Statistical Eye Diagram (.StatEye) New Model Support.

BSIM 4.6.5. BSIM SOI 4.2. HSIMHV 1.2.0. HSPICE 2007.09 - Major Enhancements in Sept 2007 Release Performance, Convergence & Accuracy Improvements. Multi-CPU.ALTER support.

Improved auto convergence. Faster netlist read-in Design for Yield - Variability Analysis. Spatial variation support. Subcircuit parameter support Board & Package Design - Signal Integrity. IBIS time step control improvement HSPICE RF – RFIC & High Speed PLL design. S-element support in Shooting Newton for spiral inductor modeling.

Spurious noise analysis Post Layout. SPEF & DSPF support New Device Model Support. HiSIM 2.4.

This tutorial shows Spice simulation of a CMOS inverter. At this point, you should have set up the environment. Otherwise, refer to.

Please note that Spectre is case sensitive unlike standard SPICE. This file, however, uses SPICE syntax, not Spectre's (notice the 'simulator lang' line, if you have the curiosity to read). Copy the following inverter source file and Spice models for MOSFETs to your working directory.

SPICE model 2. Study the netlist. The source file performs a DC analysis. If you wish to make a transient analysis, comment out the lines under 'For DC analysis only,' and remove '.' for the lines under 'For Transient analysis only.' To peform spice simulation, type the command. Spectre inv.scs 5.

To plot the results, type the command. Awd -dataDir inv.raw 6. Four windows appear. Activate 'Result Browser' window: Click left buton on inv.raw 8.

Yellow node numbers show up on the right end of the hierarchy: Click right button on nodes 2 and 3. 'Waveform Window' displays the waveform. To make a hard copy of the plot: Choose hardcopy menu from Windows menu on 'Waveform Display' window. A windows appears. Verify Laser Writer is chosen as 'Plotter Name'.

Click 'Send Plot Only to File.,' and type in the file name. Click apply to generate a postscript file. Additional Info:. For details of Spice and Spectre, refer to the online manuals.

They can be opened as:. cdsdoc &. Choose the following menus in the sequence. IC Tools - Analog and Mixed Signal Simulation. For SPICE choose 'HSPICE/SPICE Interface.'

. For Spectre choose 'Spectre User Guide.' ., but this is in Spectre's own syntax. Note that since most people are more familiar with SPICE syntax, perhaps that should be used. Also, this new example makes different simulations from the first one.

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Run Cadence setup script first. For example, with the NCSU kit, the command would be 'source NCSUsetup.csh'. Isuzu rodeo sport manual 2002. To simulate: spectre compar.scs. To view results: awd -dataDir compar.raw &.

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IMPORTANT: There must be one blank line at end of file. Spectre is case-sensitive.